VHDL 16位CPU

VHDL 16位CPU 简单的CPU设计，含有ROM,RAM,PC,指令寄存器等模块，VHDL 16位CPU 简单的CPU设计，含有ROM,RAM,PC,指令寄存器等模块，VHDL 16位CPU 简单的CPU设计，含有ROM,RAM,PC,指令寄存器等模块，VHDL 16位CPU 简单的CPU设计，含有ROM,RAM,PC,指令寄存器等模块，VHDL 16位CPU 简单的CPU设计，含有ROM,RAM,PC,指令寄存器等模块，VHDL 16位CPU 简单的CPU设计，含有ROM,RAM,PC,指令寄存器等模块，VHDL 16位CPU 简单的CPU设计，含有ROM,RAM,PC,指令寄存器等模块，

 属性            大小     日期    时间   名称
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     文件      16782  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\.xhdl3.comp.xref

     文件        402  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\.xhdl3.xref

     文件       9191  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\alu.bsf

     文件        767  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\alu.vhd

     文件       2519  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\ALUV.bsf

     文件        651  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\ALUV.v

     文件       1981  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\ALU_A1.bsf

     文件       1980  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\ALU_V.bsf

     文件       1339  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\ALU_V.vhd

     文件       5403  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\arrayreg.bdf

     文件       1743  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CCF.bsf

     文件        892  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CCF.cmp

     文件       3322  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CCF.vhd

     文件       2305  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CMP_V.bsf

     文件        784  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CMP_V.v

     文件       8390  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\cnt3.bdf

     文件       8402  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\cnt4.bdf

     文件       2156  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CNT5.bsf

     文件        942  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CNT5.cmp

     文件        356  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CNT5.qip

     文件       4542  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CNT5.vhd

     文件       8105  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\comp.bsf

     文件        991  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\comp6.vhd

     文件       5561  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CONTRL.bsf

     文件       5562  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CONTRL3.bsf

     文件       7737  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CONTRL3.vhd

     文件      19345  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CONTRL3_r.v

     文件       5562  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CONTRL4.bsf

     文件       7665  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CONTRL4.vhd

     文件       8841  2014-04-21 12:48  4_CPU_DSN\CPU_16b\EXPT_6_2 CPU16b_Verilog_SIM\CONTRL4_r.v

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