系统全局时钟控制模块的verilog实现

利用verilog编写系统时钟模块，调用dll的IP核，将输入50MHz的系统时钟信号分频或扩频成所需要的24MHz和100MHz信号，简单易行，亲测可用

 属性            大小     日期    时间   名称
----------- ---------  ---------- -----  ----
     目录           0  2018-06-19 16:29  system_ctrl\
     目录           0  2018-06-20 16:31  system_ctrl\dev\
     目录           0  2018-06-20 16:31  system_ctrl\dev\db\
     文件        4004  2018-06-20 11:47  system_ctrl\dev\db\logic_util_heursitic.dat
     文件       88920  2018-06-20 11:47  system_ctrl\dev\db\prev_cmp_System_Ctrl_Design.qmsg
     文件        1514  2018-06-20 11:47  system_ctrl\dev\db\System_Ctrl_Design.（0）.cnf.cdb
     文件         886  2018-06-20 11:47  system_ctrl\dev\db\System_Ctrl_Design.（0）.cnf.hdb
     文件        2621  2018-06-19 17:33  system_ctrl\dev\db\System_Ctrl_Design.（1）.cnf.cdb
     文件         898  2018-06-19 17:33  system_ctrl\dev\db\System_Ctrl_Design.（1）.cnf.hdb
     文件        1995  2018-06-19 17:33  system_ctrl\dev\db\System_Ctrl_Design.（2）.cnf.cdb
     文件        1246  2018-06-19 17:33  system_ctrl\dev\db\System_Ctrl_Design.（2）.cnf.hdb
     文件        1737  2018-06-19 17:33  system_ctrl\dev\db\System_Ctrl_Design.（3）.cnf.cdb
     文件        1033  2018-06-19 17:33  system_ctrl\dev\db\System_Ctrl_Design.（3）.cnf.hdb
     文件        1637  2018-06-19 17:33  system_ctrl\dev\db\System_Ctrl_Design.（4）.cnf.cdb
     文件         998  2018-06-19 17:33  system_ctrl\dev\db\System_Ctrl_Design.（4）.cnf.hdb
     文件        1991  2018-06-20 09:55  system_ctrl\dev\db\System_Ctrl_Design.（5）.cnf.cdb
     文件        1244  2018-06-20 09:55  system_ctrl\dev\db\System_Ctrl_Design.（5）.cnf.hdb
     文件        1740  2018-06-20 09:27  system_ctrl\dev\db\System_Ctrl_Design.（6）.cnf.cdb
     文件        1032  2018-06-20 09:27  system_ctrl\dev\db\System_Ctrl_Design.（6）.cnf.hdb
     文件        1653  2018-06-20 09:59  system_ctrl\dev\db\System_Ctrl_Design.（7）.cnf.cdb
     文件         995  2018-06-20 09:59  system_ctrl\dev\db\System_Ctrl_Design.（7）.cnf.hdb
     文件        2621  2018-06-20 10:42  system_ctrl\dev\db\System_Ctrl_Design.（8）.cnf.cdb
     文件         896  2018-06-20 10:42  system_ctrl\dev\db\System_Ctrl_Design.（8）.cnf.hdb
     文件        2522  2018-06-20 11:47  system_ctrl\dev\db\System_Ctrl_Design.（9）.cnf.cdb
     文件         898  2018-06-20 11:47  system_ctrl\dev\db\System_Ctrl_Design.（9）.cnf.hdb
     文件        2527  2018-06-20 11:47  system_ctrl\dev\db\System_Ctrl_Design.asm.qmsg
     文件        1419  2018-06-20 11:47  system_ctrl\dev\db\System_Ctrl_Design.asm.rdb
     文件        6976  2018-06-20 11:47  system_ctrl\dev\db\System_Ctrl_Design.asm_labs.ddb
     文件         234  2018-06-20 11:47  system_ctrl\dev\db\System_Ctrl_Design.cbx.xml
     文件         960  2018-06-20 11:47  system_ctrl\dev\db\System_Ctrl_Design.cmp.bpm
     文件       12139  2018-06-20 11:47  system_ctrl\dev\db\System_Ctrl_Design.cmp.cdb
............此处省略211个文件信息