UVM 验证测试平台搭建简单（详细）

该文档详细介绍利用UVM验证方法学库搭建system Verilog 测试验证平台的步骤和方法，我看完后感觉很好。能够很快入门UVM，是个不错的资料，分享给大家。
afunction uvm object utils(my sec (string n pernew(name task body endtask class my comp extends uvin component i uvm component utils(my comp) function new(string name, uv. component parent) super. new(name, parent) endtunction enac⊥ass class my tx extends uvm sequence item uvm object utils (my tx) function new (string name " C 2011 by Doulos Ltd. All rights reserved. All information is provided"as is" without warranty of any kind class a extends uvm ooner t uvm component utils(A) bb; //Child component / Child component function new(string name, uv: compone It parent 1 super. new(name, parent) uvm component utils(A) infunction b; / Child Ce t having p port function void build phase(uvm phase phase)i 7 Child component having q export super bui lc phase(phase)i // Factory calls to create child componen=s Furction new(string name, uvm component parent)i b= B: type id: create("b", this)i super. new(name, parent)i c-C: type id: create("c", this)i enduration endfunction -ur ction void bu-la phase(uvn phase phase)i super build phase(phase) endclass b=B:::: type id:: create(b",this) ur ction void connect phase(uvm phase phase)i ndfurction my -x txi y tx: type my -x:: type id: set type override(alt: get type ())i class my ccmp extends uvm component uvn component utils(my comp uvn aralysis port my tx)aport unction void build phase (uvm phasephase)i y =x:: type id::set inst override(alt:: get type(!, super build phase( phase) endf on task run phase(uvm phase phase) 2 C 2011 by Doulos Ltd. All rights reserved. All information is provided"as is" without warranty of any kind my tx:: type id: create(tx") aport write(tx) enatask class my seg extends uvm sequence # (my tx) lass alt tx extends my txi uvm object utils(alt tx) task bod my tx txi unction new(str-ng name =w) tx my tx:: type id: create("tx") afunction start item(tx)冫 ass会rt(tx. randomi7e()wth{cm习==0:}) constraint my constraint t data 128; endC⊥aSs lass my test extends uvm test t utils(my test Iny env envi Eurction void bu:la phase (uvm phase phase)i super build phase( phase) y override rep env my env: type id: create("env", this) enduration task run phase(uvm phasephase)i as< body seg my seg:: type id:: create(seg") repeat(n SS eg randomize()with f n=22i)) begin gstart( env. sequencer )i task y seg:: typ create("saq") start item(seg) inish it ndash C 2011 by Doulos Ltd. All rights reserved. All information is provided"as is" without warranty of any kind oration dclass run test ("my test )i class producer extends uvm component; uvn component utils(producer) / Cor figuration parameters bit param1 =0 0 tr- furction void bu-la phase (uvn phase phase) super build phase(phase)i be if( uvm config dh +(my config):: get( this config", config) param - config param param?= config. param2; param= config param; en functio class my config extends uvm objecti endal uvm object utils(my config) rand bit paramli rand int param2i n param y Other configuration parameters function new (string name -#")i uper. new(name)i enafunction endclass class my test extends uvm testi uvm component utils(my test) my env env function void build phase(uvir phase pase)i super buila phase(phase)i begi my configconfig =net / Can randomize the configuratio assert( config. randomize())i 7/ Can set individual members config. param2 =3 config param.3="filer.ame"; uvm config dh #(my corfig):: set( this, *.*producer*,"config", config)i end //A SEQUENCER is a component nv- top:: tyre id: create(env",tais)i class my sar extends uvm sequencer #(my tx)i C 2011 by Doulos ltd. All rights reserved. All information is provided"as is "without warranty of any kind uvm component uti s(my sgr) sarl. seq item export. function new(string nane, uvIT. component parenti enduration uper, new(name, parent)i endless infunction endclass // A SEQUENCE is generated dynamically class my seg extends uvm sequence # (my tx)i uvm object utils(my seq) function new ( string name =h)i class aro seg extends uvm sequence #(anc tx)i super. new(name)i uvm object utils(ano sea en习f1 nation uvn declare p sequencer(ano sgr) task body; task body my tx txi my tx:: type id: create("tx")i my txtx from -i start item(tx)i p⊥ sequencer. seg item port.get( tx frcim1)氵 assert( tx randomize()) finish item(tx) task endclass class my test extends uvm testi uvm component utils(my test task run phase(uvm phase phase)i -y sea seai // Create the sequence seg my seg:: type id: :create("seq")i // randomize it assert( sea, randomize()) // and start it on the sequencer sea. start( env. agent sgr )i enatask endclass lass ano sgr extends uvm sequencer #(ano =x uvm component utils(ano sqr uvm seq item pull port #(my tx) seq -tem porti class my driver extends uvn driver (my tx) function void build phase(uv. phase phase) uvn component utils(my driver super build phase(phase)i virtual dut i= dut vi: seq item pcrt new("seg item port", this)i infunction endclass Furction new(str: ng name, uvm component. parent)i t); end funct furction void build ph se) super build phase(phase)i class my env extends uvm env begin uvm component utils(my erv) my ccn=ig config uvn config db (virtual dut if):: get( duty my sqr sqrli dut vi) end ano sar scr2 enduration function void build phase(uvr. phase pnase)i super buila phase(phase) task run phase(uvm phase phase) 1= my sar:: type id:: create("sgrl, this)i forever sq-2=a.no sqr:: type id:: create(sqrt", this); hegin y =x txi infunction seg item port. get(tx) function void connect phase(uvn phase phase)i // Wiggle pins of DUt sq-2 seg item port connect dut vi add tx. addr C 2011 by Doulos ltd. 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All information is provided"as is "without warranty of any kind dut vi dat tx. data end endtask endclass lass my subscribe ubscriber #(my tx)i uvm component utils(my subscriber) bi int addr t da covercroup cove￥us int addr coverpcint data ndgroup Furccion called through analysis port furction void write (my tx t)i t. add: dat cover bus. samp_e()i endclass class my monitor extends uvm monitor class my env extend s uvm env uvm component utils(my monitor) uvm component ut=la(my env uvm ana l ysi s port (my tx) arorti my mmor1-Cr monitori my subscriber subscribe ri rtual dut i f dut vi Function void bu-la phase(uvm phase phase) task run phase(uvm phase phase)i super build phase( phase) monitor my monitor:: type id:: create( begin this) my tx txi subscriber my subscriber:: type id:: create( t上s) / Sense the dut pins on a clock edge end furction @(posedge dut vi clock)i tx my tx: type id: create("tx")i urction void connect phase(uvm phase phase)i dut vi, cmd monitor aport connec tx addr aut vi, addr subscriber analysis export )i ndfurction end endtask endclass extends uvm component uvm aralysis imp #(txl, A)analysis export 1 p #(tx2, B) l ass my checker extends uvm commoner t C 2011 by Doulos Ltd. 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All information is provided"as is" without warranty of any kind superdo copy(rhs); // Two incoming transaction streams Scast(rhs, rhs)i uvn analysis export #(tx1)txl export rhs, cnd uvm analysis export #(tx2)tx2 export addr rhs addr data rhs da t A ai ndfurction unction bit do compare(uvm object rhs function void connect phase(uvm phase phase)i uvm comparer comparer)i // Bind exports to two separate ch-ldren mv tx rhs txl export connect( a aralysis export bit status =1 tx2 export connect(b aralysis export )i status & super do compare(rhs, comparer)i infunction scast(rhs, rhs) tatus & comparer compare field("cmd rhs shits(cmd))i status & co parer. compare field("addr", addr, hs addr, shits(addr))i status & comparer compare field( data", data, rhs datar bits(data)) return(status)i enduration endclass function void write(my tx t)i my tx copy (t) history. push back(tx) if(! t compare(expected) uvm error("mismatch", ssformat f("Bad transact or s" t. convert2string())) uvm nfo('message type","message", UVM T oW) infunction task bod class my tx extends uvn sequence item vm test done. raise objection(this) uvm object utils (my tx) repeat(n rand int addr function string convert2string return ssfcrmatf(.); uvm test done. drop objection(this) infunction endtask function void do copy(uvm object rhs)i my tx rhs C 2011 by Doulos Ltd. All rights reserved. All information is provided"as is" without warranty of any kind as< run pnase(uvIn phase phase) phase raise abjection (this) 2009 1. 0 User's C 2011 by Doulos Ltd. All rights reserved. All information is provided"as is" without warranty of any kind