八位加法器设计

基于vivado开发平台使用Verilog实现四位加法器的设计然后再级联实现八位加法器

 属性            大小     日期    时间   名称
----------- ---------  ---------- -----  ----

     文件       3084  2018-04-07 20:59  adder\adder.cache\wt\gui_handlers.wdf

     文件       1370  2018-04-07 20:59  adder\adder.cache\wt\java_command_handlers.wdf

     文件        121  2018-04-07 20:59  adder\adder.cache\wt\project.wpc

     文件       5392  2018-04-07 20:52  adder\adder.cache\wt\synthesis.wdf

     文件        100  2018-04-07 20:51  adder\adder.cache\wt\synthesis_details.wdf

     文件       3951  2018-04-07 20:59  adder\adder.cache\wt\webtalk_pa.xml

     文件        343  2018-04-07 20:56  adder\adder.hw\adder.lpr

     文件        850  2018-04-07 20:59  adder\adder.hw\hw_1\hw.xml

     文件         59  2018-04-07 20:59  adder\adder.hw\webtalk\.xsim_webtallk.info

     文件        650  2018-04-07 20:59  adder\adder.hw\webtalk\labtool_webtalk.log

     文件       2976  2018-04-07 20:59  adder\adder.hw\webtalk\usage_statistics_ext_labtool.html

     文件       2578  2018-04-07 20:59  adder\adder.hw\webtalk\usage_statistics_ext_labtool.xml

     文件        199  2018-04-07 20:33  adder\adder.runs\.jobs\vrs_config_1.xml

     文件        385  2018-04-07 20:50  adder\adder.runs\.jobs\vrs_config_2.xml

     文件        190  2018-04-07 20:52  adder\adder.runs\impl_1\.init_design.begin.rst

     文件          0  2018-04-07 20:52  adder\adder.runs\impl_1\.init_design.end.rst

     文件        190  2018-04-07 20:52  adder\adder.runs\impl_1\.opt_design.begin.rst

     文件          0  2018-04-07 20:53  adder\adder.runs\impl_1\.opt_design.end.rst

     文件        190  2018-04-07 20:53  adder\adder.runs\impl_1\.place_design.begin.rst

     文件          0  2018-04-07 20:53  adder\adder.runs\impl_1\.place_design.end.rst

     文件        190  2018-04-07 20:53  adder\adder.runs\impl_1\.route_design.begin.rst

     文件          0  2018-04-07 20:54  adder\adder.runs\impl_1\.route_design.end.rst

     文件        189  2018-04-07 20:52  adder\adder.runs\impl_1\.vivado.begin.rst

     文件          0  2018-04-07 20:55  adder\adder.runs\impl_1\.vivado.end.rst

     文件          0  2018-04-07 20:50  adder\adder.runs\impl_1\.Vivado_Implementation.queue.rst

     文件        190  2018-04-07 20:54  adder\adder.runs\impl_1\.write_bitstream.begin.rst

     文件          0  2018-04-07 20:55  adder\adder.runs\impl_1\.write_bitstream.end.rst

     文件    2192117  2018-04-07 20:55  adder\adder.runs\impl_1\adder8bit.bit

     文件       5765  2018-04-07 20:50  adder\adder.runs\impl_1\adder8bit.tcl

     文件      21891  2018-04-07 20:55  adder\adder.runs\impl_1\adder8bit.vdi

............此处省略92个文件信息